1. Field of the Invention
The present invention relates to a semiconductor memory device including read-only memory (ROM) cells, and more particularly, to a presetting function of a sense amplifier in such a semiconductor memory device.
2. Description of the Related Art
ROM devices are broadly divided into a mask ROM device and a nonvolatile ROM device such as an erasable programmable ROM (EPROM) device and an electrically erasable programmable ROM (EEPROM) device.
In a mask ROM device, binary data "0" or a memory cell corresponds to:
the presence or absence of an enhancement type transistor; PA1 the low or high threshold voltage of a transistor; PA1 the depletion type or enhancement type of a transistor; or PA1 the presence or absence of a contact window (throughhole) which connects a transistor to one bit line.
Similarly, in an EPROM device or an EEPROM device, binary data "0" or "1" low or high threshold voltage of a transistor, which is determined by introducing carriers (electrons) into a floating gate due to a tunnel effect.
A prior art ROM device includes a memory cell array formed by ROM memory cells, a digit line for receiving read data from a selected one of the ROM memory cells, a sense amplifier for sensing a voltage at the digit line to generate a sense voltage signal, a reference circuit for generating a reference voltage signal, and a comparator for comparing the sense voltage signal with the reference voltage signal to generate an output signal. Further, an equalizer is provided between the sense amplifier and the reference circuit, to thereby enhance a read operation speed. In this case, the equalizer is operated by a so-called address transition detection signal (see: K. Imamiya et al., "A 68-ns 4Mbit CMOS EPROM with High-Noise-Immunity Design", IEEE Journal of Solid-State Circuits, Vol. 25, No. 1, pp. 72-77, Feb. 1990). This will be explained later in detail.
In the above-described prior art ROM device, however, since the digit line is precharged by the equalizer, i.e., by the sense amplifier and the reference circuit, the power dissipation thereof is increased. Particularly, when this prior art ROM device is applied to a page mode ROM device, power dissipation is further increased due to the increased number of reference circuits. Also, in this case, the increased number of reference circuits deteriorates the integration. Note that, in a page mode ROM device, if the number of reference circuits is forcibly decreased, the read operation speed is reduced.